library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity boardsim is
	port(
		SW: IN STD_LOGIC_VECTOR(17 downto 0);
		KEY: IN STD_LOGIC_VECTOR(3 downto 0);
		
		LEDR: OUT STD_LOGIC_VECTOR(17 downto 0);
		LEDG: OUT STD_LOGIC_VECTOR(8 downto 0)
	);
end boardsim;

architecture arch of boardsim is
	--signal declaration

--component declaration for entity

COMPONENT SF_rcv_interface
	PORT
	(
		reset		:	 IN STD_LOGIC;
		clk		:	 IN STD_LOGIC;
		rcv_drdreq		:	 IN STD_LOGIC;
		rcv_lrdreq		:	 IN STD_LOGIC;
		packet_finished		:	 IN STD_LOGIC;
		rcv0_data		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		rcv1_data		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		rcv2_data		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		rcv3_data		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		rcv0_length		:	 IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		rcv1_length		:	 IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		rcv2_length		:	 IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		rcv3_length		:	 IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		rcv0_qempty		:	 IN STD_LOGIC;
		rcv1_qempty		:	 IN STD_LOGIC;
		rcv2_qempty		:	 IN STD_LOGIC;
		rcv3_qempty		:	 IN STD_LOGIC;
		rcv_data		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		rcv_length		:	 OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
		port_number		:	 OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
		connection_ready		:	 OUT STD_LOGIC;
		rcv0_drdreq		:	 OUT STD_LOGIC;
		rcv1_drdreq		:	 OUT STD_LOGIC;
		rcv2_drdreq		:	 OUT STD_LOGIC;
		rcv3_drdreq		:	 OUT STD_LOGIC;
		rcv0_lrdreq		:	 OUT STD_LOGIC;
		rcv1_lrdreq		:	 OUT STD_LOGIC;
		rcv2_lrdreq		:	 OUT STD_LOGIC;
		rcv3_lrdreq		:	 OUT STD_LOGIC
	);
END COMPONENT;
	
	--output logic
	BEGIN
	COMP : SF_rcv_interface PORT MAP(
		reset		=>	NOT KEY(3),
		clk		=>	 NOT KEY(0),
		rcv_drdreq		=>	 SW(14),
		rcv_lrdreq		=>	 SW(15),
		packet_finished		=>	 NOT KEY(1),
		rcv0_data(0)		=>	 SW(0),
		rcv1_data(0)		=>	 SW(4),
		rcv2_data(0)		=>	 SW(8),
		rcv3_data(0)		=>	 SW(12),
		rcv0_length(0)		=>	 SW(1),
		rcv1_length(0)		=>	 SW(5),
		rcv2_length(0)		=>	 SW(9), 
		rcv3_length(0)		=>	 SW(13),
		rcv0_qempty		=>	 SW(2),
		rcv1_qempty		=>	 SW(6),
		rcv2_qempty		=>	 SW(10),
		rcv3_qempty		=>	 SW(14),
		rcv_data(0)		=>	 LEDG(0),
		rcv_length(3 downto 0)		=>	 LEDR(3 DOWNTO 0),
		port_number		=>	 LEDR(17 downto 16),
		connection_ready		=>	 LEDR(15),
		rcv0_drdreq		=>	 LEDR(4),
		rcv1_drdreq		=>	 LEDR(5),
		rcv2_drdreq		=>	 LEDR(6),
		rcv3_drdreq		=>	 LEDR(7),
		rcv0_lrdreq		=>	 LEDR(8),
		rcv1_lrdreq		=>	 LEDR(9),
		rcv2_lrdreq		=>	 LEDR(10),
		rcv3_lrdreq		=>	 LEDR(11)
	);	
	LEDG(1) <=  NOT KEY(0);
end arch;